A known conventional semiconductor device includes a semiconductor substrate of a first conductivity type, a pillar layer including a first semiconductor pillar sub-layer of the first conductivity type and a second semiconductor pillar sub-layer of a second conductivity type that is formed on the semiconductor substrate and has a rectangular strip-like shape in cross section, a first main electrode electrically connected to the semiconductor substrate, a semiconductor base layer of the second conductivity type formed on a surface of the first semiconductor pillar sub-layer, a second main electrode that is directly joined to a semiconductor diffusion layer of the first conductivity type selectively formed by diffusion on a surface of the semiconductor base layer and is electrically connected to the semiconductor base layer, and a gate electrode formed, with an insulating film interposed therebetween, in a region that extends from the semiconductor diffusion layer to the first semiconductor pillar sub-layer to form a channel in the semiconductor base layer between the semiconductor diffusion layer and the first semiconductor pillar sub-layer (see FIG. 15 of Patent Literature 1, for example).
For example, if two semiconductor devices, such as the MOSFET disclosed in FIG. 15 of Patent Literature 1 described above, are used to achieve synchronous rectification, and the ratio of the input capacitance “Ciss” to the feedback capacitance “Crss” of the semiconductor devices is low, charging and discharging of the capacitances can cause the gate voltage to increase to cause malfunction and turn on a semiconductor device turned off. To solve this problem, the thickness or area of the insulating layer around the gate electrode can be adjusted to adjust the input capacitance “Ciss” and the feedback capacitance “Crss”. However, such adjustment of the thickness or area of the insulating layer around the gate electrode has an influence on other characteristics, such as the threshold voltage or the withstanding voltage.